The present invention relates to integrated circuit protection methods, and in particular to methods to protect integrated circuits from external overvoltage.
ESD Protection
In MOS integrated circuits, the inputs are normally connected to drive the gate of one or more MOS transistors. (The term "MOS" is used in this application, as is now conventional, to refer to any insulated-gate-field-effect-transistor (IGFET), or to integrated circuits which include such transistors.) A longstanding problem is that electrostatic discharges (or similar externally generated voltage transients) may break down the thin gate oxide. Once the gate oxide has thus been punctured, the transistor may be permanently damaged. Thus, it has long been conventional to use protection devices on the input pins of MOS integrated circuits. Such protection devices are designed to avalanche (passing a large amount of current, and dissipating the energy of the incoming transient) before the voltage on the input pin can reach levels which would damage the gate oxide.
A variety of device structures for protecting integrated circuits against electrostatic discharge have been proposed. See, e.g., the following articles, and references cited therein, all of which are incorporated by reference:
Duvvury et al., "ESD: a pervasive reliability concern for IC technologies gies," 81 PRoc. IEEE 690 (1993); Amerasekera et al., "ESD in integrated circuits," 8 QUALITY AND RELIABILITY ENGINEERING INTERNATIONAL 259 (1992); Welsher et al., "Design for electrostatic--discharge (ESD) protection in telecommunications products, " 69 AT&T TECHNICAL JOURNAL 77 (1990); Avery, "A review of electrostatic discharge mechanisms and on-chip protection techniques to ensure device reliability," 24 J. ELECTROSTATICS 111 (1990); Greason et al., "The effects of electrostatic discharge on microelectronic devices--a review," 20 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS 247 (1984); R. N. Rountree and C. L. Hutchins, "NMOS protection circuitry, " IEEE Trans. Electron Devices, vol. ED-32, pp. 910-917, May 1985; U.S. Pat. No. 5,032,742 (Zanders), "ESD circuit for input which exceeds power supplies in normal operation;" U.S. Pat. No. 5,347,185 (Tailliet), "Protection Structure Against Latch-Up in a CMOS Circuit;" U.S. Pat. No. 5,438,213 (Tailliet), "General Protection of an Integrated Circuit against Permanent Overloads and Electrostatic Discharges;" the entire annual proceedings of the International Reliability Physics Symposia ("IRPS") for years 1980 to date; and the entire annual proceedings of the EOS/ESD symposia for years 1979 to date. PA1 Improved voltage regulator protection for on die circuitry. PA1 Reduced die area vs. some prior solutions. PA1 Low quiescent current. PA1 Flexible for circuit adjustment. PA1 Minimum difference under normal conditions.
Overvoltage from External Voltage Sources
A similar problem arises in systems using multiple voltage levels. For example, an automotive system may use a system/battery power source which is nominally .about.14V (and may, for a short time, go as high as .about.40V), but have internal components which use a regulated power source of 3.3V or 5V. In these cases, there is a risk not only of typical ESD, but that any external pin of the regulated lower-voltage system will be inadvertently shorted to the higher voltage. If this occurs, there is a significant risk of damage to the low-voltage components. To prevent this, it is preferable that an overvoltage protection circuit be integrated into the low-voltage system.
The primary problem with most current overvoltage protection schemes is the use of a diode, as in prior art FIG. 3A. This diode can cause significant voltage difference between the regulated rail and the internal rail, which could then lead to interface situations and voltage headroom problems.
Another known solution is to shunt a zener clamping diode with the internal rail, but this would need a current limiting resistor, as shown in FIG. 3B. The required resistor would also contribute to a significant voltage difference between the regulated rail and the internal rail, depending on the current passed. Both prior solutions would make it impossible to meet a low drop out specification, where the circuit output is desired to be very close to the regulated voltage input.
Innovative Internal Voltage Protection Circuit
The present application discloses an internal circuitry protection scheme which protects on-IC circuitry when an external regulator voltage pin is shorted to a higher voltage. The disclosed circuit prevents damage to the on-die circuitry that is on the internal voltage rail, by clamping the received voltage, thereby eliminating the chance of damaging the on-die circuitry. The disclosed circuit offers protection even if the voltage difference is large, but the difference remains small between the internal rail and the external regulated voltage under normal operation. This circuit is cost effective in its additional area requirements, and meets customer requirements. This circuit also works as a passive protection device, reducing the possibility for damage while unpowered.
Advantages of the disclosed methods and structures include: